ايران ويج

ABSTRACT
The ideal synthesizable design has only one clock and all its flip-flops are triggered on
its positive edge. That makes the whole flow a lot easier, from synthesis to post-route timing
analysis via DFT stages. Unfortunately, that dream is usually far from reality; the
design uses both clock edges, has latches, several internal clocks, sometimes coming from
different PLLs, and even asynchronous inputs that need to be used as edge triggers.

The purpose of this paper is to give a set of mechanisms and synthesis tips that should
get the design as close as possible to the ideal case. The clock issues are progressively
introduced; a solution is always proposed, either as a synthesizable positive edge-triggered
mechanism, or as a constraint tip, with its application requirements and its drawbacks.
Every proposition has already been used on a real design case.