(۲۹-تير-۱۳۹۳, ۰۰:۱۵:۳۲)salehjg نوشته است: [ -> ]نقل قول: والا من با اون روش شما دیگه اصلا آشنایی ندارم. فکر کنم باید یه ترم هم برم تا نحوه کار با محیط برنامه رو بلد شم.ترم؟
نقل قول: ادد کردم بازم ارور داد...1 لحظه بگم
نقل قول: باید برم استاده.؟
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Top002 is
port(
clk_in: in std_logic;
);
end Top002;
architecture Behavioral of Top002 is
signal clk_in_div : std_logic;
begin
clk_DIV0: entity work.clk_DIV
port map (
clk_in => clk_in, clk_out => clk_in_div
);
--code haye diige!
end Behavioral;
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:48:54 07/30/2014
-- Design Name:
-- Module Name: carry_look_en - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity carry_look_en is
Port ( i_add1 : in STD_LOGIC_VECTOR (3 downto 0);
i_add2 : in STD_LOGIC_VECTOR (3 downto 0);
o_result : out STD_LOGIC_VECTOR (4 downto 0));
end carry_look_en;
architecture rtl of carry_lookahead_adder_4_bit is
component module_full_adder is
port (
i_bit1 : in std_logic;
i_bit2 : in std_logic;
i_carry : in std_logic;
o_sum : out std_logic;
o_carry : out std_logic);
end component module_full_adder;
signal w_G : std_logic_vector(3 downto 0); -- Generate
signal w_P : std_logic_vector(3 downto 0); -- Propagate
signal w_C : std_logic_vector(4 downto 0); -- Carry
signal w_SUM : std_logic_vector(3 downto 0);
begin
FULL_ADDER_BIT_0 : module_full_adder
port map (
i_bit1 => i_add1(0),
i_bit2 => i_add2(0),
i_carry => w_C(0),
o_sum => w_SUM(0),
o_carry => open
);
FULL_ADDER_BIT_1 : module_full_adder
port map (
i_bit1 => i_add1(1),
i_bit2 => i_add2(1),
i_carry => w_C(1),
o_sum => w_SUM(1),
o_carry => open
);
FULL_ADDER_BIT_2 : module_full_adder
port map (
i_bit1 => i_add1(2),
i_bit2 => i_add2(2),
i_carry => w_C(2),
o_sum => w_SUM(2),
o_carry => open
);
FULL_ADDER_BIT_3 : module_full_adder
port map (
i_bit1 => i_add1(3),
i_bit2 => i_add2(3),
i_carry => w_C(3),
o_sum => w_SUM(3),
o_carry => open
);
-- Create the Generate (G) Terms: Gi=Ai*Bi
w_G(0) <= i_add1(0) and i_add2(0);
w_G(1) <= i_add1(1) and i_add2(1);
w_G(2) <= i_add1(2) and i_add2(2);
w_G(3) <= i_add1(3) and i_add2(3);
-- Create the Propagate Terms: Pi=Ai+Bi
w_P(0) <= i_add1(0) or i_add2(0);
w_P(1) <= i_add1(1) or i_add2(1);
w_P(2) <= i_add1(2) or i_add2(2);
w_P(3) <= i_add1(3) or i_add2(3);
-- Create the Carry Terms:
w_C(0) <= '0'; -- no carry input
w_C(1) <= w_G(0) or (w_P(0) and w_C(0));
w_C(2) <= w_G(1) or (w_P(1) and w_C(1));
w_C(3) <= w_G(2) or (w_P(2) and w_C(2));
w_C(4) <= w_G(3) or (w_P(3) and w_C(3));
-- Final Answer
o_result <= w_C(4) & w_SUM; -- VHDL Concatenation
end rtl;i_bit2 => i_add2(1),
i_carry => w_C(1),
o_sum => w_SUM(1),
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity d_ff_4bit_beh is
Port ( clk : in std_logic;
rst : in STD_LOGIC_VECTOR (3 downto 0);
pre : in STD_LOGIC_VECTOR (3 downto 0);
ce : in STD_LOGIC_VECTOR (3 downto 0);
d : in STD_LOGIC_VECTOR (3 downto 0);
q : out STD_LOGIC_VECTOR (3 downto 0));
end d_ff_4bit_beh;
architecture Behavioral of d_ff_4bit_beh is
begin
process (clk) is
begin
if rising_edge(clk) then
if (rst(0)='1') then
q(0) <= '0';
elsif (pre(0)='1') then
q(0) <= '1';
elsif (ce(0)='1') then
q(0)<= d(0);
end if;
if (rst(1)='1') then
q(1) <= '0';
elsif (pre(1)='1') then
q(1) <= '1';
elsif (ce(1)='1') then
q(1)<= d(1);
end if;
if (rst(2)='1') then
q(2) <= '0';
elsif (pre(2)='1') then
q(2) <= '1';
elsif (ce(2)='1') then
q(2)<= d(2);
end if;
if (rst(3)='1') then
q(3) <= '0';
elsif (pre(3)='1') then
q(3) <= '1';
elsif (ce(3)='1') then
q(3)<= d(3);
end if;
end if;
end process;
end Behavioral;(۰۶-آذر-۱۳۹۵, ۰۱:۳۴:۰۶)salehjg نوشته است: [ -> ]اگه مجبورا vhdl کار مکینی که هیچ
ولی وریلاگ راحتره..
طبق تجربه، vhdl برای پروژه های بزرگ مثل میکروکنترلر اینا دیدم که استفاده کردن..
وریلاگ هم میشه ولی به اندازه vhdl نیست...
در مورد پیشنهاد نمیدونم، در چه زمینه ای ؟ هدف هست یا از روی علاقه ؟ ...