۰۹-شهریور-۱۳۹۱, ۱۲:۱۹:۵۳
سلام
یه تاپیک خوب برای این نوع مشکلات :)
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**********************
اولی error هاست.
دومی warning هاست
با ise کار میکنم. ورژن 11
یه تاپیک خوب برای این نوع مشکلات :)
دوستان مشکل این کد من چیه؟
سنتز نمیشه....
کد:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:48:29 08/29/2012
-- Design Name:
-- Module Name: top01 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top01 is
Port ( out01 : buffer STD_LOGIC :='0';
out02 : buffer STD_LOGIC :='0';
reset : in std_logic;
clk : in STD_LOGIC);
end top01;
architecture Behavioral of top01 is
begin
process(clk,reset)
variable count: integer range 0 to 1000 :=0;
begin
if(reset = '1')then
count := count +1;
if( count >900 )then
count :=0;
if(out01 = '0') then
out01 <='1';
else
out01 <='0';
end if;
end if;
else
count:=0;
end if;
end process;
end Behavioral;کد:
FATAL_ERROR:Xst:xstrtlviewer.c:2417:1.85 - Unsupported macro type (LPM_LATCH_) in FillNodePropFromMacroBas Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.**********************
کد:
WARNING:Xst:819 - "top01.vhd" line 40: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<reset>, <out01>
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <out02> is never assigned.
WARNING:Xst:737 - Found 1-bit latch for signal <out01>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. Found 10-bit adder for signal <count$add0000> created at line 44. Found 10-bit comparator greater for signal <out01$cmp_gt0000> created at line 45. Summary:اولی error هاست.
دومی warning هاست
با ise کار میکنم. ورژن 11
