and1 Project Status (04/01/2014 - 20:55:22) | |||
Project File: | test3.xise | Parser Errors: | No Errors |
Module Name: | and1 | Implementation State: | Programming File Generated |
Target Device: | xc3s400-5pq208 |
|
No Errors |
Product Version: | ISE 14.7 |
|
No Warnings |
Design Goal: | Balanced |
|
All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of 4 input LUTs | 1 | 7,168 | 1% | ||
Number of occupied Slices | 1 | 3,584 | 1% | ||
Number of Slices containing only related logic | 1 | 1 | 100% | ||
Number of Slices containing unrelated logic | 0 | 1 | 0% | ||
Total Number of 4 input LUTs | 1 | 7,168 | 1% | ||
Number of bonded IOBs | 3 | 141 | 2% | ||
Average Fanout of Non-Clock Nets | 1.00 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Mon Mar 31 20:33:59 2014 | 0 | 0 | 0 | |
Translation Report | Current | Tue Apr 1 20:57:36 2014 | 0 | 0 | 0 | |
Map Report | Current | Tue Apr 1 20:57:43 2014 | 0 | 0 | 2 Infos (2 new) | |
Place and Route Report | Current | Tue Apr 1 20:57:49 2014 | 0 | 0 | 1 Info (1 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Tue Apr 1 20:57:53 2014 | 0 | 0 | 6 Infos (6 new) | |
Bitgen Report | Current | Tue Apr 1 20:57:58 2014 | 0 | 0 | 1 Info (1 new) |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
Post-Synthesis Simulation Model Report | Current | Tue Apr 1 20:55:21 2014 | |
WebTalk Report | Current | Tue Apr 1 20:57:59 2014 | |
WebTalk Log File | Current | Tue Apr 1 20:58:07 2014 |