and1 Project Status (04/01/2014 - 20:55:22)
Project File: test3.xise Parser Errors: No Errors
Module Name: and1 Implementation State: Programming File Generated
Target Device: xc3s400-5pq208
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 1 7,168 1%  
Number of occupied Slices 1 3,584 1%  
    Number of Slices containing only related logic 1 1 100%  
    Number of Slices containing unrelated logic 0 1 0%  
Total Number of 4 input LUTs 1 7,168 1%  
Number of bonded IOBs 3 141 2%  
Average Fanout of Non-Clock Nets 1.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Mar 31 20:33:59 2014000
Translation ReportCurrentTue Apr 1 20:57:36 2014000
Map ReportCurrentTue Apr 1 20:57:43 2014002 Infos (2 new)
Place and Route ReportCurrentTue Apr 1 20:57:49 2014001 Info (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentTue Apr 1 20:57:53 2014006 Infos (6 new)
Bitgen ReportCurrentTue Apr 1 20:57:58 2014001 Info (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Synthesis Simulation Model ReportCurrentTue Apr 1 20:55:21 2014
WebTalk ReportCurrentTue Apr 1 20:57:59 2014
WebTalk Log FileCurrentTue Apr 1 20:58:07 2014

Date Generated: 04/02/2014 - 13:22:34