Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3
OS Platform: NT Target Device: xc3s400
Project ID (random number) 331d0b7c353b461fb5aa2436986099f0.DC7304F4A4EA4AC287FC1921C298891C.1 Target Package: pq208
Registration ID __0_0_0 Target Speed: -5
Date Generated 2014-04-01T20:57:59 Tool Flow ISE
 
User Environment
OS Name Microsoft , 32-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i3 CPU M 370 @ 2.40GHz CPU Speed 2466 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=3
  • AGG_IO=3
  • AGG_SLICE=1
  • NUM_4_INPUT_LUT=1
  • NUM_BONDED_IOB=3
  • NUM_SLICEL=1
NetStatistics
  • NumNets_Active=6
  • NumNodesOfType_Active_DOUBLE=1
  • NumNodesOfType_Active_DUMMY=2
  • NumNodesOfType_Active_DUMMYESC=2
  • NumNodesOfType_Active_INPUT=3
  • NumNodesOfType_Active_IOBOUTPUT=2
  • NumNodesOfType_Active_OMUX=3
  • NumNodesOfType_Active_OUTPUT=1
SiteStatistics
  • IOB-DIFFM=2
SiteSummary
  • IOB=3
  • IOB_INBUF=2
  • IOB_OUTBUF=1
  • IOB_PAD=3
  • SLICEL=1
  • SLICEL_G=1
 
Configuration Data
IOB
  • O1=[O1_INV:0] [O1:1]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:1]
IOB_PAD
  • DRIVEATTRBOX=[12:1]
  • IOATTRBOX=[LVCMOS25:3]
  • SLEW=[SLOW:1]
 
Pin Data
IOB
  • I=2
  • O1=1
  • PAD=3
IOB_INBUF
  • IN=2
  • OUT=2
IOB_OUTBUF
  • IN=1
  • OUT=1
IOB_PAD
  • PAD=3
SLICEL
  • G1=1
  • G2=1
  • Y=1
SLICEL_G
  • A1=1
  • A2=1
  • D=1
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • netgen -intstyle ise -ar Structure -tm <design> -w -dir netgen/synthesis -ofmt vhdl -sim <fname>.ngc <fname>.vhd
  • vhdtdtfi -prj test3 -o <fname>.vhi -module <design> -template <fname>.tft -deleteonerror -lib work <fname>.vhd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s400-pq208-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 1 1 0 0 0 0 0
map 3 2 0 0 0 0 0
netgen 1 1 0 0 0 0 0
ngdbuild 3 3 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 2 2 0 0 0 0 0
xst 9 9 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pn_db_npw_device_properties.htm ( 2 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/and1
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2014-03-30T22:06:42
PROP_intWbtProjectID=DC7304F4A4EA4AC287FC1921C298891C PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_selectedSimRootSourceNode_behav=work.and1 PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true PROP_DevFamily=Spartan3
PROP_DevDevice=xc3s400 PROP_DevFamilyPMName=spartan3
PROP_DevPackage=pq208 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-5 PROP_PreferredLanguage=VHDL
FILE_VHDL=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_LUT2=1 NGDBUILD_NUM_OBUF=1
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_LUT2=1 NGDBUILD_NUM_OBUF=1
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s400-5-pq208 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=8
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5